Full-water test and burn-in mechanism

ABSTRACT

Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate. In a further aspect a translated wafer is disposed over the translator socket such that the tester side of the translator is in contact with the translator socket; and the heat spreading cushion is disposed over the backside of the translated wafer. In a still further aspect, the substrate includes signal communication means, such as but not limited to, an edge connector adapted to couple to various controller circuits, which are typically disposed on a printed circuit board.

CROSS-REFERENCE TO RELATED APPLICATIONS

This non-provisional patent application is a reissue application forU.S. Pat. No. 7,719,298, issued from U.S. patent application Ser. No.12/272,717, filed on Nov. 17, 2008, entitle “Full-Wafer est and Burn-InMechanism”, which is a continuation of U.S. application Ser. No.11/810,950, filed 6 Jun. 2007 now U.S. Pat. No. 7,453,277, entitled“Methods and Apparatus For Full-Wafer Test And Burn-In Mechanism”; whichclaimed the benefit of U.S. Provisional Application No. 60/811,508,filed 6 Jun. 2006, entitled “Methods and Apparatus For Full-Wafer TestAnd Burn-In Mechanism”; the entirety of both are hereby incorporated byreference.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor test equipment,and more particularly relates to testing integrated circuits atpredetermined temperatures prior to those integrated circuits beingsingulated.

BACKGROUND

Subsequent to fabrication of wafers having many integrated circuitsformed thereon, it is a common practice to test the functionality andelectrical characteristics of those integrated circuits while still inwafer form. That is, well-known semiconductor processes are used toperform a variety of operations on a wafer, culminating in the formationof a plurality of integrated circuits, which are typically cut apart sothat individual integrated circuits may be put into protective packages,or otherwise incorporated into products. However, in order to preventthe packaging, or other use, of integrated circuits that may havemanufacturing defects, the wafer is coupled to one or more test systemsto verify that the integrated circuits contained in that wafer, performaccording to the specifications associated with those integratedcircuits.

Conventionally, electrical connection between a test system and theindividual integrated circuits, sometimes referred to as die, is madevia a probe card. These probe cards provide a first mechanism toelectrically interface, or connect, with a test system, and a secondmechanism to physically touch and electrically connect with the verysmall contact pads exposed at a top surface of each integrated circuit.This second mechanism typically consists of probes, sometimes referredto as probe needles, that must be precisely shaped, aligned, and thetips of which must be positioned in a co-planar manner so that the probetips all touch the contact pads of an integrated circuit without beingshort of the target pad, and without driving too deeply into the pad.

Subsequent to testing the individual integrated circuits on the wafer,those integrated circuits that have successfully passed testing, arepackaged and then re-tested. This re-testing of the packaged integratedcircuits, sometimes referred to as “final test”, may be used todetermine whether the assembly operations of packaging have resulted ina part that does not function properly, or may be used for convenientlytesting the integrated circuits in environmentally challenging settings,such as for example, elevated temperatures. Operating, or testing, anintegrated circuit at elevated temperature is sometimes referred to asburn-in. Such burn-in testing may identify integrated circuits that donot function according their specifications. Unfortunately, detectingfailures after an integrated circuit has been packaged results in highercosts for a manufacturer than if such a failure could have been detectedwhile the integrated circuit was still in wafer form.

What is needed are methods and apparatus for wafer-level, that ispre-singulation, testing of the integrated circuits on a wafer that isoperated within a user defined temperature range.

SUMMARY OF THE INVENTION

Briefly, assemblies in accordance with the present invention include asubstrate, such as a printed circuit board, with a first array ofcontact pads disposed thereon; a guide ring structure disposed on thesubstrate and at least partially surrounding the first array of contactpads; translator socket disposed on the first array of contact pads, thetranslator socket adapted to receive the tester side of a translatedwafer; a thermally conductive, conformal, heat spreading cushion adaptedto be disposed over the backside of a wafer; a cover plate adapted tofit over the first array of contact pads, align with the guide ringstructure, contain within it the various components disposed over firstarray of contact pads, and removably attach to the substrate; and abolster plate adapted to removably attach to a second side of thesubstrate.

In a further aspect of the present invention, a translated wafer isdisposed over the translator socket such that the tester side of thetranslator is in contact with the translator socket; and the heatspreading cushion is disposed over the backside of the translated wafer.

In a still further aspect of the present invention, the substrateincludes signal communication means, such as but not limited to, an edgeconnector adapted to couple to various controller circuits, which aretypically disposed on a printed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exterior view of a burn-in oven conventionally used forproviding a high-temperature, or burn-in, environment for packagedsemiconductor components.

FIG. 2 shows two conventional circuit boards that are used forconventional burn-in processes.

FIG. 3 shows a conventional burn-in board, which contains an array ofcomponents to be tested, or at least powered, while at an elevatedtemperature in a burn-in oven.

FIG. 4 is an illustration of a conventional burn-in board loaded withcomponents for testing at elevated temperatures, and further shows aconventional controller board, which, in operation, is coupled to theburn-in board, and which transmits and receives various signals to andfrom the burn-in board.

FIG. 5 illustrates a conventional arrangement of stacks of burn-inboard/controller board pairs disposed within a burn-in oven system.

FIG. 6 illustrates a wafer-level test and burn-in assembly, inaccordance with the present invention, and further shows a pair ofcontroller boards suitable for coupling to the wafer-level test andburn-in assembly.

FIG. 7 illustrates an arrangement of stacks of wafer-level test andburn-in assemblies, in accordance with the present invention, eachassembly coupled to corresponding controller boards.

FIG. 8 is an exploded view of the wafer-level test and burn-in assemblyincluding a base cover, a first edge-extended substrate, a firsttranslator socket, a first translator, a first wafer, a first headspreader, a heat source, a second heat spreader, a second wafer, asecond translator, a second edge-extended substrate, and a top cover.

FIG. 8A is a side view of the wafer translator.

DETAILED DESCRIPTION

Various embodiments of the present invention provide methods andapparatus for conducting burn-in of wafer form, i.e., unsingulated,integrated circuits. These various embodiments are suitable for use withconventional controller boards but eliminate the need for burn-in ovens.

Reference herein to “one embodiment”, “an embodiment”, or similarformulations, means that a particular feature, structure, operation, orcharacteristic described in connection with the embodiment, is includedin at least one embodiment of the present invention. Thus, theappearances of such phrases or formulations herein are not necessarilyall referring to the same embodiment. Furthermore, various particularfeatures, structures, operations, or characteristics may be combined inany suitable manner in one or more embodiments.

Terminology

Reference herein to “circuit boards”, unless otherwise noted, isintended to include any type of substrate upon which circuits may beplaced. For example, such substrates may be rigid or flexible, ceramic,flex, epoxy, FR4, or any other suitable material.

Pad refers to a metallized region of the surface of an integratedcircuit, which is typically used to form a physical connection terminalfor communicating signals to and/or from the integrated circuit.

The expression “wafer translator” refers to an apparatus facilitatingthe connection of I/O pads (sometimes referred to as terminals, pads,contact pads, bonding pads, chip pads, or test pads) of unsingulatedintegrated circuits, to other electrical components. It will beappreciated that “I/O pads” is a general term, and that the presentinvention is not limited with regard to whether a particular pad of anintegrated circuit is part of an input, output, or input/output circuit.A wafer translator may be disposed between a wafer and other electricalcomponents. The As illustrated in FIG. 8A, the wafer translator includesa substrate having two major surfaces, an inquiry-side 803a and awafer-side 803b, each surface having terminals disposed thereon, andelectrical pathways disposed through the substrate to provide forelectrical continuity between at least one terminal on a first surfaceand at least one terminal on a second surface. The wafer-side 803b ofthe wafer translator has a pattern of terminals at a second scale d2that matches the layout of at least a portion of the I/O pads of theintegrated circuits on the wafer. The wafer translator, when disposedbetween a wafer and other electrical components, makes electricalcontact with one or more I/O pads of a plurality of integrated circuitson the wafer, providing an electrical pathway therethrough to the otherelectrical components. The wafer translator is a structure that is usedto achieve electrical connection between one or more electricalterminals that have been fabricated at a first scale, or dimension d1 atthe inquiry-side 803a, and a corresponding set of electrical terminalsthat have been fabricated at a second scale, or dimension d2 at thewafer-side 803b. The wafer translator provides an electrical bridgebetween the smallest features in one technology (e.g., pins of a probecard at scale d1) and the largest features in another technology (e.g.,bonding pads of an integrated circuit at scale d2). For convenience,wafer translator is referred to simply as translator where there is noambiguity as to its intended meaning.

The expression “translated wafer” refers to a wafer that has a wafertranslator attached thereto, wherein a predetermined portion of, or allof, the contact pads of the integrated circuits on the wafer are inelectrical contact with corresponding electrical connection meansdisposed on the wafer side of the translator. Typically, the wafertranslator is removably attached to the wafer. Removable attachment maybe achieved by means of vacuum, or pressure differential, attachment.

The expressions “burn-in socket for wafers”, “wafer burn-in socket”, and“translator socket”, refer to a component adapted to be disposed upon afirst array of contact pads, to make electrical contact with theindividual terminals of that first array of contact pads, and to makeelectrical contact with a plurality of contact pads on the topside, alsoreferred to as the “tester side”, of a wafer translator. The translatorsocket comprises an insulating body with contact pads disposed on eachmajor surface, and further having interconnections through thatinsulating body to provide electrical connection between the contactpads on one side with corresponding pads on the other side. Although theterm “socket” is used, the translator socket is not limited to aconfiguration in which insertion of terminals into the translator socketis required. In other words, the translator socket may take the form ofan interposer with contact pads on each major surface thereof, and inwhich electrical contact is made by urging counterpart contact pads, orterminals, of the substrate and/or the non-wafer-side of the translatorinto contact with the translator socket.

The terms chip, integrated circuit, semiconductor device, andmicroelectronic device are sometimes used interchangeably in this field.The present invention relates to the manufacture and test of chips,integrated circuits, semiconductor devices and microelectronic devicesas these terms are commonly understood in the field.

FIGS. 1-5 illustrate conventional components and arrangements used forburin-in operations with packaged integrated circuits.

Referring to FIG. 4, a burn-in board 400 includes integrated circuits401 coupled to sockets 402, which are disposed on burn-in board 400.Burn-in board 400 further includes edge connector 403, which is adaptedto couple to controller board 404.

FIG. 5 shows stacks of burn-in boards 400 paired with controller boards404, where the stacks are disposed within a conventional burn-in oven500.

Various embodiments of the present invention provide methods andapparatus for wafer-level burn-in that allows for use of conventionalcontroller boards and burn-in ovens.

Referring to FIG. 6, a wafer-level burn-in board assembly 700, inaccordance with the present invention, is shown juxtaposed to controllerboard 404. Wafer-level burn-in board assembly 700, includes a translatedwafer (not shown), under cover 701, disposed on a wafer-level burn-inboard 702. Wafer-level burn-in board assembly 700, may alternatively bereferred to as a wafer-level burn-in assembly.

FIG. 7 shows stacks of wafer-level burn-in assemblies 700 paired withcontroller boards 404, where the stacks are disposed within burn-in oven500.

Referring to FIG. 8, an exploded view of wafer-level burn-in assembly700 is shown. Wafer-level burn-in assembly 700 of FIG. 8 includes abolster plate 807, a wafer-level burn-in board 701, a guide ringstructure 806, a first array of contact pads 805, a wafer burn-in socket804, a wafer translator 803, a wafer 802, a heat spreader 801, and acover 800.

As shown in FIG. 8, a wafer-level burn-in board 702 has a first areawithin which are disposed a first array of contact pads 805. Contactpads 805 are adapted to make electrical contact with a corresponding setof contact pads disposed on a wafer burn-in socket 804. At least aportion of contact pads 805 are coupled, by way of electricallyconductive pathways, to various contact pads of the edge connector ofburn-in board 701. It will be appreciated that an electrical pathwaybetween any one of contact pads 805 and a corresponding edge connectorpad, may be made by a single conductive line, or by a combination ofconductive line segments coupled disposed on two or more layers andelectrically connected by vias, or plated through holes, or any othersuitable means of electrically connecting conductive lines on differentlayers of a printed circuit or other substrate.

Heat spreader 801 is a thermally conductive cushion characterized by theability to transfer heat between at least the cover and the wafer. Heatspreader 801 is typically disposed such that it is in physical contactwith both the backside of wafer 802 and with cover 800. In this way,heat from the burn-in oven can be transferred through cover 800 to wafer802. Typically, heat transfer through heat spreader 801 is notuni-directional, and therefore heat from wafer 802 may also betransferred through heat spreader 801 to cover 800 when the differencein temperatures supports such transfer.

Still referring to FIG. 8, guide ring structure 806 is disposed onwafer-level burn-in board 702 outside the first area. In theillustrative embodiment of FIG. 8, guide ring structure 806 is round,but the present invention is not limited to any particular geometriclayout, and may take forms such as, but not limited to, ovals, squaresand rectangles. Guide ring structure 806 is a continuous structure inFIG. 8, but alternative embodiments may be implemented wherein guidering structure 806 is discontinuous. Guide ring structure 806 provides aseat for cover 800, and provides holes through which cover 800 may bescrewed to bolster plate 807. Bolster plate 807 acts as a mechanicalstiffener, and may further act to provide a means, such as threadedholes, for the attachment of cover 806 by screws. Bolster plate 807 istypically made of metal, but is not so limited, and may be fabricatedfrom any material or combination of materials capable of providing theaforementioned characteristics of stiffening and/or anchoring theattachment of cover 800. It is noted that a variety of alternativeattachment configurations may be used to attach cover 800 and bolsterplate 807 to wafer-level burn-in assembly 700.

In one embodiment of the present invention, a wafer-level burn-inassembly, includes:

a circuit board having a first major surface and a second major surface;

a first plurality of contact pads disposed in a first area of the firstmajor surface of the circuit board, the first plurality of contact padsarranged in first pattern;

a guide ring disposed on the first major surface of the circuit boardsuch that the guide ring is outside the first area;

a wafer burn-in socket having a first major surface and a second majorsurface, the first major surface having a plurality of contact padsarranged in a second pattern that matches the first pattern, the secondmajor surface having a plurality of contact pads arranged in a thirdpattern, the first major surface of the wafer burn-in socket disposed onthe circuit board;

a wafer translator having a first major surface and a second majorsurface, the first major surface having a plurality of contact padsarranged in a fourth pattern that matches the third pattern, the firstmajor surface of the wafer translator disposed on the wafer burn-insocket;

a wafer attached to the second major surface of the wafer translator;

a heat spreader disposed against a side of the wafer facing away fromthe translator; and

a cover disposed over the heat spreader.

In another embodiment, a wafer-level burn-in assembly includes:

a circuit board having a first major surface and a second major surface;

a first plurality of contact pads disposed in a first area of the firstmajor surface of the circuit board, the first plurality of contact padsarranged in first pattern;

a guide ring disposed on the first major surface of the circuit boardsuch that the guide ring is outside the first area;

a wafer burn-in socket having a first major surface and a second majorsurface, the first major surface having a plurality of contact padsarranged in a second pattern that matches the first pattern, the secondmajor surface having a plurality of contact pads arranged in a thirdpattern, the first major surface of the wafer burn-in socket disposed onthe circuit board;

a wafer translator having a first major surface and a second majorsurface, the first major surface having a plurality of contact padsarranged in a fourth pattern that matches the third pattern, the firstmajor surface of the wafer translator disposed on the wafer burn-insocket;

a wafer removably attached to the second major surface of the wafertranslator;

a heat spreader disposed against a side of the wafer facing away fromthe translator; and

a cover disposed over the heat spreader and in physical contact with theguide ring.

CONCLUSION

Various embodiments of the present invention include apparatus andmethods for providing wafer level, i.e., pre-singulation, testing ofintegrated circuits, at predetermined temperatures.

Embodiments of the present invention may find application in the fieldof semiconductor circuit testing.

An advantage of some embodiments of the present invention includestesting integrated circuits at elevated temperatures while still inwafer form in a manner that is compatible with existing burn-inequipment, including burn-in ovens and controller boards, that areadapted for burn-in testing of individually packaged integratedcircuits.

It is to be understood that the present invention is not limited to theembodiments described above, but encompasses any and all embodimentswithin the scope of the subjoined Claims and their equivalents.

What is claimed is:
 1. A wafer-level burn-in assembly, comprising: acircuit board having a first major surface and a second major surface; afirst plurality of contact pads disposed in a first area of the firstmajor surface of the circuit board, the first plurality of contact padsarranged in first pattern; a guide ring disposed on the first majorsurface of the circuit board such that the guide ring is outside thefirst area; a wafer burn-in socket having a first major surface and asecond major surface, the first major surface having a plurality ofcontact pads arranged in a second pattern that matches the firstpattern, the second major surface having a plurality of contact padsarranged in a third pattern, the first major surface of the waferburn-in socket disposed on the circuit board; a wafer translator havinga first major surface and a second major surface, the first majorsurface having a plurality of contact pads arranged in a fourth patternthat matches the third pattern, the first major surface of the wafertranslator disposed on the wafer burn-in socket; a wafer attached to thesecond major surface of the wafer translator; a heat spreader disposedagainst a side of the wafer facing away from the translator; a coverdisposed over the heat spreader; and a controller board coupled to thecircuit board.
 2. The wafer-level burn-in assembly of claim 1, whereinthe controller board and the circuit board are disposed within a burn-inoven.
 3. The wafer-level burn-in assembly of claim 2, further comprisinga first plurality of circuit boards coupled to corresponding ones of afirst plurality of controller boards, each of the coupled pairs ofcircuit boards and controller boards are disposed within the burn-inoven and spatially arranged to form one or more stacks.
 4. Thewafer-level burn-in assembly of claim 1, further comprising a bolsterplate disposed on the second major surface of the circuit board.
 5. Thewafer-level burn-in assembly of claim 1, wherein the guide ringcomprises two or more discontinuous segments.
 6. The wafer-level burn-inassembly of claim 4, wherein the guide ring has holes therethroughthrough which the cover is screwed to the bolster plate.
 7. Thewafer-level burn-in assembly of claim 1, wherein the circuit board hasan edge connector comprising a plurality of contact pads each of whichis electrically coupled to a corresponding one of the first plurality ofcontact pads disposed in the first area of the first major surface ofthe circuit board.
 8. A wafer-level burn-in assembly, comprising: acircuit board having a first major surface and a second major surface; afirst plurality of contact pads disposed in a first area of the firstmajor surface of the circuit board, the first plurality of contact padsarranged in first pattern; a guide ring disposed on the first majorsurface of the circuit board such that the guide ring is outside thefirst area; a wafer burn-in socket having a first major surface and asecond major surface, the first major surface having a plurality ofcontact pads arranged in a second pattern that matches the firstpattern, the second major surface having a plurality of contact padsarranged in a third pattern, the first major surface of the waferburn-in socket disposed on the circuit board; a translated wafer havinga first surface comprising a wafer backside and a second surfacecomprising a wafer translator tester-side; a heat spreader disposedagainst a side of the wafer facing away from the translator; a coverdisposed over the heat spreader; a controller board coupled to thecircuit board.
 9. The wafer-level burn-in assembly of claim 8, whereinthe controller board and the circuit board are disposed within a burn-inoven.
 10. The wafer-level burn-in assembly of claim 9, furthercomprising a first plurality of circuit boards coupled to correspondingones of a first plurality of controller boards, each of the coupledpairs of circuit boards and controller boards are disposed within theburn-in oven and spatially arranged to form one or more stacks.
 11. Thewafer-level burn-in assembly of claim 8, further comprising a bolsterplate disposed on the second major surface of the circuit board.
 12. Thewafer-level burn-in assembly of claim 8, wherein the guide ringcomprises two or more discontinuous segments.
 13. The wafer-levelburn-in assembly of claim 11, wherein the guide ring has holestherethrough through which the cover is screwed to the bolster plate.14. The wafer-level burn-in assembly of claim 8, wherein the circuitboard has an edge connector comprising a plurality of contact pads eachof which is electrically coupled to a corresponding one of the firstplurality of contact pads disposed in the first area of the first majorsurface of the circuit board.
 15. A wafer-level burn-in assembly,comprising: a circuit board having a first major surface and a firstplurality of contact pads arranged in a first pattern at a first area ofthe first major surface; an interposer having a first major surfacefacing the first major surface of the circuit board, the first majorsurface of the interposer having a second plurality of contact padsarranged in a second pattern that corresponds to the first pattern ofthe circuit board, and a second major surface of the interposer, thesecond major surface having a third plurality of contact pads arrangedin a third pattern; and a wafer translator having a first major surfacefacing the second major surface of the interposer, the first majorsurface of the wafer translator having a fourth plurality of contactpads arranged in a fourth pattern that corresponds to the third patternof the interposer, and a second major surface positioned to face towarda wafer; a heat spreader disposed toward the wafer translator; a coverdisposed over the heat spreader; and a guide ring adjacent to the cover,the guide ring having holes for fasteners.
 16. A wafer-level burn-inassembly, comprising: a circuit board having a first major surface and afirst plurality of contact pads arranged in a first pattern at a firstarea of the first major surface; an interposer having a first majorsurface facing the first major surface of the circuit board, the firstmajor surface of the interposer having a second plurality of contactpads arranged in a second pattern that corresponds to the first patternof the circuit board, and a second major surface of the interposer, thesecond major surface having a third plurality of contact pads arrangedin a third pattern; a wafer translator having a first major surfacefacing the second major surface of the interposer, the first majorsurface of the wafer translator having a fourth plurality of contactpads at a first scale and arranged in a fourth pattern that correspondsto the third pattern of the interposer, and a second major surfacehaving a fifth plurality of contact pads at a second scale andpositioned to electrically contact for burn-in testing semiconductordies of a wafer, wherein the first scale is larger than the secondscale; a heat spreader facing toward the wafer translator; and a coverdisposed over the heat spreader.
 17. The wafer-level burn-in assembly ofclaim 16, further comprising a bolster plate facing the circuit boardopposite from the first major surface of the circuit board, the bolsterplate attached to the cover.
 18. The wafer-level burn-in assembly ofclaim 17, further comprising a guide ring between the bolster plate andthe cover, the guide ring having holes for fasteners connecting thebolster plate and the cover.
 19. The wafer-level burn-in assembly ofclaim 16, further comprising a controller board coupled to the circuitboard.
 20. The wafer-level burn-in assembly of claim 16, furthercomprising a plurality of edge connectors on the circuit board, theplurality of edge connectors in electrical contact with thecorresponding plurality of contact pads on the circuit board.
 21. Amethod for wafer-level burn-in, comprising: aligning a circuit board, aninterposer and a wafer translator, the circuit board having a firstmajor surface and a first plurality of contact pads arranged in a firstpattern at a first area of the first major surface; the interposerhaving a first major surface facing the first major surface of thecircuit board, the first major surface of the interposer having a secondplurality of contact pads arranged in a second pattern, and a secondmajor surface having a third plurality of contact pads arranged in athird pattern; the wafer translator having a first major surface facingthe second major surface of the interposer, the first major surface ofthe wafer translator having a fourth plurality of contact pads at afirst scale and arranged in a fourth pattern, and a second major surfacehaving a fifth plurality of contact pads at a second scale andpositioned to electrically contact for burn-in testing semiconductordies of a wafer, wherein the first scale is larger than the secondscale, and wherein aligning includes: aligning at least one of the firstand second patterns with the other of the first and the second pattern,and aligning at least one of the third and fourth patterns with theother of the third and fourth patterns; disposing a heat spreaderagainst the wafer translator; and disposing a cover over the heatspreader.
 22. The method of claim 21, further comprising: disposing abolster plate against the circuit board opposite from the first majorsurface of the circuit board, and attaching the bolster plate to thecover.
 23. The method of claim 21, further comprising disposing a guidering between the bolster plate and the cover, wherein the guide ring hasholes for the fasteners connecting the bolster plate and the cover. 24.The method of claim 21, further comprising operably coupling acontroller board to the circuit board through a plurality ofcorresponding edge connectors on the controller board and the circuitboard.